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There have been several efforts on run-time mapping of applications on multiprocessor-systems-on-chip. These traditional efforts perform either on-the-fly processing or use design-time analyzed results. However, on-the-fly processing often leads to low-quality mappings, and design-time analysis becomes computationally costly for large-size problems and require huge storage for large number of applications...
We present a novel reconfigurable hardware architecture for interpolation filtering in high efficient video coding that adapts to run-time changes of the number of interpolation filter calls and thereby provides a high potential of energy efficiency. It employs a picture-based prediction scheme to estimate the number of interpolation filter calls at run-time by monitoring the group of pictures history...
Hybrid Distributed Video Coding (Hybrid-DVC) is an emerging compression paradigm for resource-constrained embedded devices, like wireless video sensor nodes. This paper presents a low-overhead energy-aware Hybrid-DVC with an adaptive computation offloading scheme. Our scheme offloads the workload of multiple video encoding devices concurrently to a high-end decoder device to minimize the overall system...
Advancement in technology has complemented the increased complexity of state-of-the-art video coding standards by providing high-performance multimedia platforms. This has resulted in non-negligible computational reliability issues, especially with respect to soft errors. This paper motivates the dire need towards computationally Reliable Video Coding (ReVC) on modern hardware platforms. We highlight...
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