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This brief presents a pseudorandom number generator that requires very low resources from the hardware design point of view. It is based on a chain of digital accumulators whose coefficients are varied by an auxiliary low-complexity linear feedback shift register. We present a predictability and periodicity analysis of the sequences generated by the proposed architecture to show that the system is...
We present the design and the validation by means of state-of-the-art randomness tests of a high-quality true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as a set of interleaved chaotic maps. Developing the circuit design relying on pipeline A/D technology, which is ubiquity used in all mixed signal systems, allow us to design a fast...
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