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This paper presents a high-performance, low-cost, and double node upset (DNU) tolerant latch design. The latch mainly constructs from a 3-input Muller C-element at the output stage and a single node upset resilient cell for keeping data, and the cell mainly consists of triple mutual feedback 2-input Muller C-elements, thus the latch is DNU tolerant. Using fewer CMOS transistors, clock gating technique,...
This paper presents a novel low cost and double node upset tolerant latch design in 22nm CMOS technology. The latch mainly comprises a single node upset resilient cell which feeds back to a 3-input Muller C-element at output stage. Simulation results demonstrate the double node upset tolerance and an 81.2% area-power-delay product saving for the latch design on average.
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