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Reconfigurable Field Programmable Gate Arrays (rFPGAs) are employed extensively in spacecraft electronic systems to implement low-power adaptable systems that provide high density functionality. A challenge that must be tackled during system design is their high susceptibility to radiation induced Single Event Upsets (SEUs). A burst of energized particles may cause extensive damage to circuits. Even...
Grid-computing technology is used to solve large or complex computational problems on distributed computational resources belonging to multiple organizations regardless of their geographical locations. In this paper, we introduce an integration of the SAFORAH geospatial data grid, provided by the Canadian Forest Service, and the computational grids, offered by the University of Victoria and National...
Heterogeneity of resources can not be ignored while scheduling application task graphs in grid environment. In this paper, a list-based task scheduling algorithm, called scheduling with heterogeneity using critical path (SHCP) for grid computing system is presented. Some other scheduling algorithms such as HEFT use mean execution time based b-level for deciding task priority and ignore the importance...
Task duplication based scheduling algorithms generate shorter schedules without sacrificing efficiency but leave the computing resources over consumed due to the heavily duplications. In this paper, we try to optimize the duplications after generating a schedule without affecting the overall schedule length (makespan). Here, we suggested two workflow scheduling algorithms with economical duplication...
Within-die parameter variations can cause wide delay distribution among similar functional units in superscalar processors. Conventionally, the frequency of operation is reduced to accommodate the slowest unit, which in turn degrades throughput. We present a low-overhead design technique that sets the operating frequency in a superscalar processor based on the faster units and allows more cycles for...
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing. In this paper, we present the design, implementation and evaluation of a continuum of software-based routers on the MIT RAW microprocessor. The routers presented in this paper explore 1) several design choices for mapping the routing functions to...
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