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This Field Programmable Gate Array (FPGA) based digital controller has been developed to improve the output of the frequency converter using Hardware Description Language. An attempt has been made to analyze converters using three modulation techniques namely sinusoidal pulse width modulation (SPWM), delta modulation (DM) and trapezoidal modulation (TM) to reduce the harmonics. It has been found that...
Reconfigurable Field Programmable Gate Arrays (rFPGAs) are employed extensively in spacecraft electronic systems to implement low-power adaptable systems that provide high density functionality. A challenge that must be tackled during system design is their high susceptibility to radiation induced Single Event Upsets (SEUs). A burst of energized particles may cause extensive damage to circuits. Even...
In this paper a digital controller has been designed and implemented on field programmable gate array (FPGA) to generate the trigger pulses for a trapezoidal modulated cycloinverter using hardware description language. Trigger requirements are obtained for single-phase centre tapped transformer configuration. With successively improving reliability and performance of digital controllers, the digital...
This paper proposes FPGA based space vector modulated (SVM) trigger controller that may be applied to a frequency converter used for high speed electrical drives, speed control of AC motor, induction heating, fluorescent lighting, ballast, high frequency power supplies and so on. To generate space vector pulse width modulated trigger pulses for the converter pperipheral input-output and FPGA interfacing...
MEMOCODE Design Contest challenged teams to implement the architecture for a unique type of Deep Packet Inspector called CANSCID. This paper describes this unique problem statement, and the motivation for choosing it. This paper is followed by short descriptions prepared by individual teams detailing their particular approach to solving the problem.
Application-specific ICs have been traditionally used to support the high computational and data rate requirements in medical ultrasound systems, particularly in receive beamforming. Utilizing the previously developed efficient front-end algorithms, in this paper, we present a simple programmable computing architecture, consisting of a field-programmable gate array (FPGA) and a digital signal processor...
When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve injecting spare resources. However, these methods use predetermined spare placement that is not optimized for each netlist. This is the first work (to the best of our knowledge) that addresses the problem of fault tolerance for...
Traditionally, application-specific integrated circuits (ASICs) are used for supporting the computational and data rate requirements of medical ultrasound systems. Utilizing the previously-developed efficient front-end algorithms and the continuing advances in solid state devices, we developed a hybrid programmable architecture to support core ultrasound signal processing. With the advent of new-...
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