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A 8 GByte/s single-ended parallel transceiver is implemented in a 0.18 mum standard CMOS with a current-balanced pseudo-differential signaling for high-speed memory interface. With a segmented group-inversion coding, 16-bit data is encoded to 20 pins for dramatic reduction of simultaneous switching noise which has been a bottleneck in high-speed parallel links. The proposed pseudo-differential signaling...
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