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Estimating the dynamic powers is crucial for power and energy efficient chip designs. With increasing variability from manufacture processes, dynamic powers can manifest significant variations due to uncertainties in device geometry and delay variations. In this paper, we propose a new statistical dynamic power estimation method considering the spatial correlation in process variation. We first show...
This paper proposes a new architecture-level thermal modeling method to address the emerging thermal related analysis and optimization problem for high-performance multi-core microprocessor design. The new approach builds the thermal behavioral models from the measured or simulated thermal and power information at the architecture level for multi-core processors. Compared with existing behavioral...
As the power density increases exponentially, the runtime regulation of operating temperature by dynamic thermal management (DTM) becomes necessary. This paper proposes two novel approaches to the thermal analysis at the chip architecture level for efficient DTM. The first method, i.e., thermal moment matching with spectrum analysis, is based on observations that the power consumption of architecture-level...
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