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A K-band low-noise amplifier (LNA) is designed and fabricated in a standard 0.18 μm CMOS technology. A design method of CMOS LNA is used to render the optimum source resistance (Ropt) close to 50 Ω and Zin=Zopt* by using small devices and small bias currents. This LNA chip achieves a peak gain of 13.5 dB and a noise figure of 4.7 dB at 24 GHz. The supply voltage and current are 1 V and 8.3 mA, respectively...
LINC can achieve linear amplification by using high-efficiency amplifiers. This work presents an all-digital LINC signal component separator (SCS) including the phase calculation digital signal processing and two digital-control phase shifters (DCPSs). With the duplicate DCPSs, a pre-calibration scheme is introduced to guarantee the codeword-to-phase linearity and accuracy under different PVT conditions...
A phase-locked loop (PLL)-based frequency synthesizer at 5 GHz is designed and fabricated in 0.18-mum CMOS technology. The power consumption of the synthesizer is significantly reduced by using an injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. The synthesizer chip consumes 18 mW of power, of which only 3.93 mW is consumed by the voltage-controlled...
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