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In this paper, we propose a capacitor-less 1T-DRAM structure with the pass-way trench for improving the Retention Time (RT). We have improved the device fabrication process to form the pass-way trench of the structure which combines the Vertical Channel and the Gate-All-Around structure (PTVCT). The memory operation and its attractive performance in terms of programming window, retention time, and...
This paper presents a highly scalable π-shaped source/drain (π-S/D) quasi-silicon-on-insulator (SOI) MOSFET and summarizes its preliminary characteristics compared with the recessed S/D SOI MOSFET and international technology roadmap for semiconductors (ITRS) roadmap values. SiGe-Si epitaxial growth, Si and SiGe etching, growth of epitaxial Si, and selective SiGe removal are used to form the π-S/D...
We present a new vertical sidewall MOSFET with embedded gate (EGVMOS) to reduce the parasitic capacitance which is the major disadvantage in a conventional VMOS. According to simulations, our EGVMOS can not only achieve about 86.34% and 54.76% reduction at Cgd at VDs = 0.05 V and 1.0 V respectively, but also improves the device reliability due to suppressed kink effects, in comparison with a conventional...
In this work, we present a novel vertical MOSFET with embedded gate structure and try to overcome the challenges mentioned above by modifying the junction depth. Therefore, four types of vertical sidewall MOSFETs with embedded gate (EVGMOS) are also demonstrated and called the EVGMOS having lightly-doped drain (LDD) w/o or w/ 2.5 nm Si etching after gate formation and non-LDD w/o or w/ 2.5 nm Si etching...
In this study, we propose a novel polysilicon thin-film transistor with multi-trenched body (MTB TFT). According to the ISE-TCAD simulations, our proposed MTB TFT gets a steep subthreshold swing (S.S.), a reduced drain-induced barrier lowering (DIBL), a lower drain off-state leakage, and a higher ION/IOFF ration, in comparison with a conventional poly-Si TFT. In addition, due to the MTB scheme, the...
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