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A 2-Gb/s integrating decision-feedback equalization (DFE) receiver was implemented for a four-drop single-ended DRAM interface channel by using a 0.25- mum CMOS process. The receiver combines both DFE and integration operations in a single receiver circuit so that the DFE operation reduces the intersymbol interference and the integration operation reduces the high-frequency noise. The DFE operation...
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