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This paper presents a 5 Gb/s adaptive equalizer that compensates for the FR-4 channel loss of 14 dB at 2.5 GHz. This equalizing filter uses low-voltage zero generators (LVZGs) to generate high-frequency tunable gain boosting without inductors. The power detector combines current steering techniques and a pre-amplifier circuit to enhance the voltage swing. This design consumes 17.6 mW (excluding the...
A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with 0.5V supply voltage.
This paper describes a 2GS/s 10 bit DAC with a supply voltage lower to 1 volt. It has been realized in a 90-nm 1P9M CMOS technology. A novel high precision active cascode mirror circuit is presented. Provided the headroom is not affected, operating the current source in the triode region, the precision of the current source array can be obtained. In addition, the demand of low analog/digital supply...
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