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A 10b 120MS/s pipeline ADC is implemented in a 45nm CMOS process. Three-stage amplifiers based on RNMC and multi-path zero cancellation techniques are employed in the SHA and two MDACs. A re-configurable three-stage switched amplifier is shared between adjacent MDACs without series switches and memory effects. A charge redistributed input sampling network properly handles single-ended or differential...
A 12-bit 1.2 V 160 MS/s pipeline ADC for high-definition video systems is presented. The proposed multipath frequency-compensation technique enables the conventional RNMC-based three-stage amplifier to achieve a stable operation at a sampling rate of 160 MS/s. The measured differential and integral nonlinearities of the prototype ADC implemented in a 65 nm CMOS process are less than 0.69 LSB and 1...
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