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The rms timing jitter of a phase-locked loop (PLL) is calculated and minimized analytically from the VCO phase noise and the in-band phase noise plateau with and without digital baseband correction in an OFDM system. Subsequently, we present an integrated wideband frequency synthesizer in a 130 nm SiGe BiCMOS technology. An 8.7GHz-11.8GHz PLL using only one VCO is followed by a frequency sixtupler...
A frequency divider providing quadrature outputs up to 30GHz is presented. Rms phase error and rms clock jitter are discussed in the context of OFDM systems, where the usual phase error correction in the digital baseband processor is included. A measurement technique for the static phase error between the in-phase and quadrature signal is proposed using an integrated single-sideband mixer in conjunction...
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