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Two 10-Gb/s inductorless clock and data recovery (CDR) circuits using different gated digital-controlled oscillators (GDCO) are presented. A digital frequency calibration is adopted to save the power consumption and chip area. They have been fabricated in 0.18-mum CMOS process. By using the complementary gating technique, the first CDR circuit occupies an active area of 0.16 mm2 and draws 36 mW from...
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