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We propose a framework to quickly analyze track congestion inside each g-cell at the global routing stage. A distinguishing feature of our framework compared to prior work is estimating the locations of vias and partial track utilization by a global segment inside each g-cell for a given global routing solution. We integrate this model with a proposed track assignment algorithm which we show can more...
This work offers a framework for predicting the delays of individual design paths at the post-silicon stage which is applicable to post-silicon validation and delay characterization. The prediction challenge is mainly due to limited access for direct delay measurement on the design paths after fabrication, combined with the high degree of variability in the process and environmental factors. Our framework...
Cloud computing for EDA requires a client to send problem instances containing confidential design information to an untrusted distributed network. To preserve the design information in such a framework, this work focuses on obfuscating the global routing problem modeled as an Integer Linear Program (ILP) for large industry benchmarks. Multiple transformations are introduced in a proposed framework...
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