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This paper presents a fully integrated self-quenched super-regenerative impulse-FM-UWB transceiver architecture for wireless body area networks. The design architecture consists of two different LC self-quenched oscillators tuned at 3.5GHz and 4.5GHz. In transmitting mode, both oscillators are turned on and off to generate impulse-FM-UWB data pattern. In receiving mode, these oscillators act as self-quenched...
In this paper, a high speed fully differential second generation current conveyor (FDCCII+) is presented. The proposed FDCCII+ is based on using fully differential buffer and class AB push-pull output stage with a new standby current control circuitry. The circuit is realized using 90 nm CMOS TSMC technology model under 1.2 V single supply voltage. The proposed realization of FDCCII+ input differential...
This paper presents measurement results on voltage and power efficient CMOS fully integrated rectifiers. Floating gate (FG) techniques are used to reduce the threshold voltage and thus the voltage drop over the rectifier. A three transistor single-poly FG diode is presented as basic element for half and full wave rectifiers. The rectifiers are implemented using a 0.35 mum high voltage CMOS technology...
This paper describes the design of voltage controlled oscillator (VCO) with a low-power static frequency divider. The new LC-VCO replaces one of the NMOS of a conventional differential LC-VCO with a PMOS, which reduces power dissipation to the half and allows operation at reduced supply voltages. Based on a 0.13um UMC CMOS process, the VCO is simulated using 0.8V supply voltage. It is demonstrated...
This paper presents a fully differential and single ended amplifier design in a standard 0.35 mum CMOS twin well process, targeted to ultra low voltage applications down to 0.5 V. By utilizing bulk-driven PMOS transistors as an input-differential pair a rail-to-rail input common mode range (ICMR) is achieved. Novel CMFB structures in combination with a new amplifier topology allow to achieve high...
The conventional common-gate low-noise amplifier (CGLNA) exhibits a relatively high noise figure (NF) at low operating frequencies relative to the MOSFET fT, which has limited its adoption even though its superior linearity, input matching, and stability compared to the inductively degenerated (CS-LNA). The design of a low-power inductorless LNA using a capacitive cross-coupled (CCC) gm -boosting...
This paper explores the reliability of single-poly floating gates in 0.13 mum CMOS technology. Charge retention times before and after wear-out are measured. Channel interface degradation is evaluated through flicker noise measurements. The results show that deep submicron single-poly floating gates can store analog information with high precision for several months. While this disqualifies them from...
This paper presents improved integrated CMOS rectifiers using floating gate (FG) transistors. These FG rectifiers have a larger output voltage compared to standard realizations and work also at high input frequencies, which is essential for telemetric applications in the MHz range. Single-poly FGs are used, which can be produced in standard CMOS processes without special process options. The simulated...
A decaying pulse shape DAC architecture for continuous-time (CT) SigmaDelta modulators is introduced. The DAC reduces the clock jitter sensitivity while putting only moderate design constrains on the respective integrators. The impact of clock jitter on the entire SigmaDelta modulator is computed and verified by electrical and behavioral simulations. In order to illustrate also the low-power benefits,...
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