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The analysis of self-heating effect in a SOI LDMOS device under an ESD stress is presented in this paper. TCAD tools are used as the platform to explore the physical process of the bulk LDMOS device and the influence of buried oxide layer inserted in the substrate. Simulation results uncover that the buried oxide layer degrades the current-handling ability and changes the lattice temperature distribution...
Four-terminal and three-terminal asymmetrical n-type LDMOS (asym-nLDMOS) devices are investigated in 0.18μm 40V SOI BCD technology. To improve normal asym-nLDMOS devices ESD robustness, an additional p-sink implant is added beneath their source/drain diffusion regions. Transmission line pulse measured results show that the novel asym-nLDMOS devices have a suitable triggering voltage and 30–48% improvement...
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