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Power consumption is becoming a concern in programmable logic design as the size and performance of modern FPGAs increase. Data-parallel applications can work on different parallelism level so as to achieve different performance. This paper presents an investigation into the best parallelism degree-operating frequency tradeoff in order to find the optimum number of instances for each parallelizable...
We propose in this paper, a timing analysis of dynamic partial reconfiguration (PR) applied to a NoC (network on chip) structure inside a FPGA. In the context of a SDR (software defined radio) example, PR is used to dynamically reconfigure a baseband processing block of a 4G telecommunication chain running in real-time (data rates up to 100 Mbps). The results presented show the validity of our methodology...
A cognitive radio is the final point of software-defined radio platform evolution : a fully reconfigurable radio that changes its communication modules depending on network and/or user demands. His definition on reconfigurability is very broad and we only focus on the heterogeneous reconfigurable hardware platform for cognitive radio. software defined radio (SDR) basically refers to a set of techniques...
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