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We present a detailed theoretical analysis to motivate GeSn for CMOS logic. High quality GeSn films have been obtained on Ge-on-Si using a CVD process. A novel surface passivation scheme is presented to achieve record low trap densities at high-ĸ/GeSn interface. Using the novel surface passivation method, combined with a low thermal budget device fabrication process, n-channel MOSFETs on GeSn with...
Our theoretical investigation reveals GeSn nMOSFETs to outperform Ge. For the first time, we fabricate nMOSFETs on GeSn and identify interface trap density, poor n-type dopant activation, channel compressive strain to limit performance in our devices. Improvement in surface passivation is achieved by introducing Ge cap on GeSn. Further enhancements in GeSn nMOSFETs can be obtained by employing implant...
In this paper, we describe the unique scaling challenges, critical sources of variation, and the potential trench leakage mechanisms of 32nm trench capacitors that utilize high-к/metal electrode materials. This is the first eDRAM technology that has successfully integrated high-к and metal films as part of the trench capacitor. In addition, these films are found to be fully compatible with front-end...
With growing semiconductor integration, the reliability of individual transistors is expected to rapidly decline in future technology generations. In such a scenario, processors would need to be equipped with fault tolerance mechanisms to tolerate in-field silicon defects. Periodic online testing is a popular technique to detect such failures; however, it tends to impose a heavy testing penalty. In...
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leading to increasing operating temperatures and current densities. Given that most wearout mechanisms that plague semiconductor devices are highly dependent on these parameters, significantly higher failure rates are projected...
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