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In this paper a 12bit 10GSps current-steering digital-to-analog converter (DAC) in 280GHz fT 0.7um InP HBT technology is presented. The DAC core works in a double-sampling way, which reduces the maximum clock frequency by half. The double-sampling switch is separated to reduce the inter-symbol-interference. An improved current steer switch architecture is adopted to enhance high frequency dynamic...
This paper describes a 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 µm complementary BiCMOS SiGe process. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T&H to improve the dynamic performance of the individual sub-ADCs and to reduce both the converter error rate and the complexity of the required interleaving background calibration algorithms. It achieves...
A 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 µm complementary BiCMOS SiGe process is presented. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T/H to improve the dynamic performance of the individual sub-ADCs and to reduce both the complexity of the required interleaving background calibration algorithms and the error rate. It achieves an SFDR of 79...
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