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On-chip MOS decoupling capacitors (DECAPs) are widely used to reduce power supply noise. Designing DECAP in nanotechnology designs provides many challenges. In this paper first it is shown that all of these challenges are functions of the DECAP channel length. Then, we propose a method for optimizing the channel length of MOS DECAPs. The technique is applied to 45 nm and 32 nm technology nodes and...
In this paper, a low-power high-performance logic style for low-voltage CMOS technologies is presented. The style is based on modifying a high-speed yet low-power logic family called feedthrough logic (FTL) style which has been previously proposed in the literature. The proposed style which is called parallel FTL (PFTL) overcomes the shortcoming of the FTL for low-voltage applications. To assess the...
In this paper, a statistical approach for the optimal design of 6-T FinFET based SRAM cells considering the statistical distributions of gate length and silicon thickness of its transistors is presented. The corresponding statistical correlations of these two parameters are also considered. In this method, proper back-gate voltages for the SRAM transistors which maximize the yield against read, write,...
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