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This paper presents two novel methods for on-chip serial communication in which the clocks of the transmitter and the receiver are generated with two separate ring oscillators. These oscillators are identical, although they can have a small frequency difference. In the first method, a strobe line that toggles exactly once with every frame of n-bit data is used to activate the oscillators. Local counters...
In this paper, we introduce a new topology for network on chips which is named multi-level mesh topology. The multi-level mesh topology is basically similar to the 2D-mesh with this difference that we have several meshes that have some common routers. This architecture reduces the latency and the dynamic power consumption in NoCs and can improve the communication throughput in high traffic applications...
In this paper inter metal capacitors of ground wires are considered, for the first time in Elmore delay calculations of clock distribution interconnect networks. Analytical models for capacitance calculation of inter metal wires which are exponentially tapered are presented. In addition, the tapering of the ground wire for reducing this delay is proposed. The results show that by a exponentially tapering...
In this paper, we propose a mesochronous scheme for communication over serial buses in network on chips (NoC). The technique, which removes metastability errors in mesochronous communications, makes use of only one strobe line with the bus. The strobe line toggles once with every frame of the data. In the suggested method, the frequencies of the transmitter and the receiver are independent with some...
Two constituencies of the underlying routing techniques are output and input selections. In this paper, we propose a routing model for avoiding congestion areas within regular two-dimensional on-chip networks which takes advantage of both output and input selections. This model is based on congestion aware route selection (CARS) technique which uses load information of neighboring switches. The simulation...
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