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Existing state-of-the-art realizable RC reduction methods may not be suitable for scalable power grid reductions due to the fast growing computational complexity and the large number of ports. In this work, we present a scalable power grid reduction method for reducing large-scale flip-chip power grids based on recent spectral graph sparsification techniques. The first step of the proposed approach...
Gate oxide breakdown is a key factor limiting the useful lifetime of an integrated circuit. Unfortunately, the conventional approach for full chip oxide reliability analysis assumes a uniform oxide-thickness for all devices. In practice, however, gate-oxide thickness varies from die-to-die and within-die and as the precision of process control worsens an alternative reliability analysis approach is...
The continuing VLSI technology scaling leads to increasingly significant power supply fluctuations, which needs to be modeled accurately in circuit design and verification. Meanwhile, the huge size of power grid requires its analysis to be fast and highly scalable. Algebraic multigrid (AMG) has been recognized as a promising approach for fast power grid analysis. We propose several techniques to improve...
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