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A new SigmaDelta modulator architecture is proposed that shapes DAC mismatches in a manner similar to quantization noise shaping, allowing operation with low oversampling ratios and compact logic. The concept is demonstrated in a fourth-order cascaded system running at a clock frequency of 500 MHz and digitizing input frequencies as high as 31 MHz with 80-dB dynamic range. Fabricated in 90-nm CMOS...
Recent work on ADCs targeting sampling rates of hundreds of MHz with resolutions in the range of 10 to 11 b has faced speed limitations with a single channel or employed interleaving, but with a relatively high power dissipation or low SNDR. This paper introduces a calibration technique that, together with a high-speed opamp topology, allows a single channel to operate at 500 MHz and digitize a 233...
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