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The saturation of a critical gate voltage at 2-2.4 V for SiON with thickness < 1.6 nm (EOT < 1.4 nm) extends the role of digital breakdown (BD) in prolonging progressive BD at nominal voltages. As a result, the post-BD gate leakage degradation rate, which is extrapolated from a high voltage using the conventional approach, is highly overestimated, warranting one to revise the post-BD reliability...
One chip solution for SMPS (switch mode power supply) has been drawing great attention of the designers with its green mode standby power and high efficiency in the AC-DC adaptor and LED lighting applications. The UHV (ultra-high voltage) foundry process, which enables the integration solution for green compliance SMPS, is proposed in this paper. The technology integrated low voltage CMOS (5 V), medium...
This paper investigates the influence of the N-type buried layer (NBL) layout and LOCOS space on the ESD performance and trigger voltage of the lateral DMOS (LDMOS) device. Without adequate LOCOS spacing, LDMOS is vulnerable to ESD damage. If the LOCOS space is sufficiently wide, adding NBL structure can further improve LDMOS ESD performance significantly. This is because NBL can switch the current...
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