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A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO2 based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and Tinv values of ˜5 Å and ˜8 Å respectively for both n and pMOS devices. The drive currents at Ioff=100 nA/μm with VDD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further...
The extraordinary optical transmission of light through a metallic nano-slit surrounded by groove corrugations can further be increased by optimizing the geometric parameters including the period of the corrugations, the period which has been set to be equal to the surface-plasmon wavelength in most of the previous works. By a global optimization, we are able to enhance the transmission efficiency...
We are reporting for the first time on the use of simple resist-based selective high-k dielectric capping removal processes of La2O3, Dy2O3 and Al2O3 on both HfSiO(N) and SiO2 to fabricate functional HK/MG CMOS ring oscillators with 40% fewer process steps compared to our previous report [1]. Both selective high-k removal (using wet chemistries) and resist strip processes (using NMP and APM) have...
We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by...
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