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HW/SW co-emulation technique combing software simulation with hardware acceleration is one of the popular techniques for SOC verification, where interrupt-based communication mechanism is usually utilized. However, communication overhead will be resulted from data exchange between hardware side and software side at every cycle. A stream-mode based HW/SW co-emulation technique is proposed and presented...
Efficient and reliable verification system is requested for a system-on-chip (SOC) design before it is committed to production. The intention of the paper is to judge whether our hardware/software (HW/SW) co-verification system can handle SOC verification and provide the necessary performance in terms of co-verification speed and throughput. A finite impulse response (FIR) filter is utilized as a...
With the growing System-on-a-chip (SOC) design complexity, SOC test and verification has become a major bottleneck. In this context, efficient and reliable test and verification system are requested for SOC design before a SOC is committed to production. HW/SW co-emulation system combing software simulation with hardware acceleration is one of dominant systems, where interrupt-based communication...
Field programmable gate arrays (FPGAs) have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software (HW/SW) co- verification technique for FPGA test is proposed and presented in the paper. Taking advantage of flexibility and observability of software in conjunction with high-speed...
Hierarchy communication channel in transaction-level hardware/software co-emulation system for system-on-a-chip (SOC) verification is proposed in the paper. The hierarchy communication channel consists of physical layer, transport layer, transaction layer and application layer. In the paper, research for the channel focuses on communication protocol for transport layer, hardware and software for physical,...
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