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Fault tolerance capabilities are becoming a fundamental requirement in many designs. Improving these systems' dependability under demanding environmental and operating conditions requires new techniques that use concurrent error detection (CED) strategies to guarantee data integrity. The system-level algorithmic CED methodology uses selective redundancy for online monitoring of system-level properties,...
A new methodology is proposed to increase the robustness of pipeline-based circuits. The goal is to improve signal integrity in the presence of power-supply voltage (VDD) and/or temperature (T) variations, without degrading circuit performance. In the proposed methodology, we dynamically control the instant of data capture (the clock edge trigger) in key memory cells, according to local VDD and/or...
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