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This paper deals with the design of an LC Voltage Controlled Oscillators using MHS SCMOS3 0.5 μm process. A sizing method is proposed to meet the WiFi and Bluetooth standards requirement. The layout of the circuit with CADENCE environment has been accomplished. Based on this layout, post layout simulations were performed and circuit improvement has been proposed in order to overcome parasites drawback.
A CMOS quadrature VCO has been designed in a 0.35 mum CMOS process. Using a combination of switched binary-weighted capacitors and standard varactors, this VCO achieves a 59% tuning range with a control voltage ranging from -0.25 to 0.75 V. The phase-noise varies within the tuning range from -131.3 dBc/Hz to -121.2 dBc/Hz at 1 MHz frequency offset. The circuit consumes only 9.37 mW at 2.71 GHz and...
We propose a heuristic for the optimal sizing of LC VCO. The heuristic is an algorithm driven methodology that allows us determining optimal sizes of inductors, bias current and channel widths that minimizes the VCOpsilas phase noise. The proposed optimization methodology was applied to size a cross-coupled differential voltage controlled oscillator. This latter, designed using AMS 0.35 mum technology,...
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