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The main challenge of Low Temperature (LT) Solid Phase Epitaxy (SPE) is the dopant deactivation during post activation anneal. For the first time, we demonstrate that, for LT-SPE activated Boron (B) on thin SOI substrates, B deactivation can be well controlled during post anneal at 400 °C–600 °C. This is achieved by locating the preamorphization induced end of range defects close to the Buried OXide...
For the first time, ultra low IOFF (16.5 pA/mum) and high IONN,P (2.27 mA/mum and 1.32 mA/mum) currents are obtained with a multi-channel CMOSFET (MCFET) architecture on SOI with a metal/high-K gate stack. This leads to the best ION/IOFF ratios ever reported: 1.4 times 108 (0.8 times 108) for 50 nm n- (p-) MCFETs. We show, based on specifically developed integration process, characterization methods...
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