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An all-digital fast-locking programmable DLL-based clock generator is presented. By resetting the output clock every two input clock periods, the initial minimal delay constraint in the conventional architecture is eliminated. Compared with the previous work, the short locking time is also achieved. The proposed circuit has been fabricated in 0.35-mum CMOS process and occupies the active area of 0...
This paper presents an novel configuration of balanced frequency InGaAs pseudomorphic high electron mobility transistor (PHEMT) monolithic microwave integrated circuit (MMIC) tripler with Ka-band output frequency (39 GHz). A resonant LC filter is used to eliminate the fundamental frequency and a phase delay line is employed to suppress the second harmonic. By using a class B transistor bias point...
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