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Static Random Access Memories (SRAMs) are key components of modern VLSI designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. Analysis performed at the "schematic" level can be deceiving as it ignores the interdependence between the implementation layout and the resulting electrical performance. We present...
With technology scaling, process constraints and imperfections result in significant variation of post-Si performance and stability of SRAM from designed/target pre-Si parameters. Modification/ re-optimization of SRAM cell and/or tuning of process parameters to meet target performance and stability are limited by area constraints and involve several technology ramp-up cycles. For reducing access failures,...
Dual-VT CMOS is an effective way to reduce leakage power in high-performance VLSI circuits. In this paper, we explore the technology design space for dual-threshold voltage transistor design in deep sub-100 nm technology nodes. We propose a technique of achieving high-VT devices - longer gate sidewall offset spacers to increase the channel length without increasing the printed gate length. Effectiveness...
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