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With the nano-scale technology, a system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes the complexity of SOC testing is much higher than testing conventional VLSI chips. One of the test challenges of SOCs is test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time....
With the nano-scale VLSI technology and system-on-chip (SOC) design methodology, the reliability has become one major challenge in SOCs. Especially, embedded memory cores heavily impact on the reliability of SOCs. Error detection and correction (EDAC) techniques are well-known methodologies for detecting and correcting soft errors of random access memories. However, conventional EDAC techniques cannot...
We consider offline testing, design-for-testability, and diagnosis for fast Fourier transform (FFT) networks. A practical FFT chip can contain millions of gates, so effective testing and fault-tolerance techniques usually are required in order to guarantee high-quality products. We propose M-testability conditions for FFT butterfly, omega, and flip networks at the double-multiply-subtract-add (DMSA)...
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