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Modem complex system-on-chips (SOCs) need infrastructure IPs to test, diagnosis, and repair embedded memories. This paper presents an infrastructure IP (IIP) for repairing multiple RAMs in SOCs. The proposed IIP can perform parallel test for multiple memories, and serial diagnosis or repair for one memory each time. Especially, the proposed IIP can execute various redundancy analysis algorithms. We...
With the nano-scale technology, a system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes the complexity of SOC testing is much higher than testing conventional VLSI chips. One of the test challenges of SOCs is test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time....
With the nano-scale VLSI technology and system-on-chip (SOC) design methodology, the reliability has become one major challenge in SOCs. Especially, embedded memory cores heavily impact on the reliability of SOCs. Error detection and correction (EDAC) techniques are well-known methodologies for detecting and correcting soft errors of random access memories. However, conventional EDAC techniques cannot...
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