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ANoC (Asynchronous Network-on-Chip) has been developed to solve problems of large number of cores in SoC (System-on-Chip) by giving asynchronism to every core. This new architecture requires new Testing methods different from the existing SoC Test, and it freshly needs the test of router and routing networks. This paper first offers high-speed testing architecture that tests more than one routers...
Low-power electronic circuit design for VLSI (Very Large Scale Integrated) testing is one of key design issues since power consumption is increased dramatically during test operations due to heavy transitions. Scan chain reordering has been one of the efficient low-power test technology to solve this problem. In this paper, we propose a new dynamic scan cell reordering technique that improves power...
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