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In this paper, the dividing ratio changeable digital phase locked loop (DCPLL) using the VCO as the base clock source is proposed. In this circuit, the ratio of output jitter is not greatly influenced for the input signal. Also, the lock-in range can be widely compared with the conventional method.
A simple circuit technique to realize current controlled oscillator (CCO) with two low-impedance input terminals is presented. By suitably setting two input signals, the linear frequency-current relation of the proposed CCO can be either positive or negative slope in the same circuit configuration. The oscillating output frequency proportional to the difference between two input currents can be also...
In this paper, the dividing ratio changeable digital phase locked loop (DCPLL) which is difficult to receive the effect of the input phase noise is proposed. This circuit can realize the characteristic of a wide lock-in range and a fast pull-in.
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