The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Low energy semi-serial on-chip communication link is to be designed. This link is designed using high speed serialization/deserialization and pulse dual rail encoding techniques. The link also consists of wave-pipelined differential pulse current-mode signaling to maintain the high speed data intake from the serializer. The energy efficiency of the proposed semi-serial link, which consists of bit...
Modern IC design and manufacturing techniques are growing such that the transistor count on a single chip escalates exponentially with complex Embedded and DSP cores in it. Hence, testing of such complex ICs are extremely challenging. It is a well-known fact that test power is several times higher than functional power. Today's Ultra-Low Power devices in deep sub-micron technologies used for embedded...
In the nano scaled transistors integration era, interconnection of IP blocks and data exchange among the IP blocks are crucial concerns in System on Chip (SoC). Network-on-Chip (NoC) is an on-chip communication methodology proposed to resolve the increased interconnection problems in SoC. In deep sub-micron regime, 3D NoC becomes an emerging research area in recent years as the three dimensional (3D)...
Latest VLSI circuits face the problem of power dissipation not only in design phase but also during testing phase. Power dissipation during testing may be increased up to three times more than that during normal operation. Testing power, testing time and test area overhead are the critical parameters to be optimized for large and complex VLSI circuits. Scan architectures are widely used in testing...
Design for low power testing is primary concern in modern VLSI circuits. In this paper a novel Test Pattern Generator (TPG) is proposed which is more suitable for Built In Self Test (BIST) architecture, used for testing of VLSI circuits. The objective of the BIST is to reduce power consumption during testing of VLSI circuits. In CMOS devices 80% of power consumption is due to switching activity occurred...
Design for low power testing is primary concern in modern VLSI circuits. In this paper a novel test pattern generator (TPG) is proposed which is more suitable for built in self test (BIST) architecture, used for testing of VLSI circuits. The objective of the BIST is to reduce power consumption during testing of VLSI circuits. In CMOS devices 80% of power consumption is due to switching activity occurred...
This paper emphasizes on a VLSI design for SIRM fuzzy processor in biomedical application. A novel approach aims to identify and design a simple robust fuzzy system with minimum number of fuzzy rules to classify the epilepsy risk level of diabetic patients from cerebral blood flow and EEG signals is discussed in this paper. Four different types of fuzzy models are designed and tested with 200 patients...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.