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In application base environment using Wireless Sensor Network (WSNs), mobility sink and node plays a key role in concern with topological changes affecting on the bandwidth utilization, energy consumption and delay. Due to the scarcity of available resources, it demands the solution with a better reduction in delay and energy consumption for increased slot utilization and reduced collisions. The paper...
As the days go by, the innovation in the technology is growing faster and smaller chips with more complexity in the design and implementation. Design of adders is prime importance in any given embedded application; hence the design of reliable and efficient adder on a VLSI based embedded application matters. In this paper we primarily deal with the construction of high speed adder circuits. Design...
Data collection and transmission are the fundamental operations of Wireless Sensor Networks (WSNs). A key challenge in effective data collection and transmission is to schedule and synchronize the activities of the nodes with the global clock. This paper proposes the Bandwidth Efficient Hybrid Synchronization Data Aggregation Algorithm (BESDA) using spanning tree mechanism (SPT). It uses static sink...
Wireless Sensor Networks (WSNs) are used for monitoring and data collection purposes. A key challenge in effective data collection is to schedule and synchronize the activities of the nodes with global clock. This paper proposes the Synchronized Data Aggregation Algorithm (SDA) using spanning tree mechanism. It provides network-wide time synchronization for sensor network. In the initial stage algorithm...
In the Wireless Sensor Networks, (WSNs) a key challenge is to schedule the activities of the mobile node for improvement in throughput, energy consumption and delay. This paper proposes efficient schedule based data aggregation algorithm using node mobility (SDNM). It considers the cluster-based myopic and non-myopic scheduling scheme for conflict free schedule based on the current and next state...
Super harmonic division at low power consumption in unilaterally injection locked current controlled ring oscillator system has been explored. Frequency divider for PLL output stage divides a 2.0GHz PLL clock by 2 while consuming just 68uW from a 1.2V power supply. Current Controlled Ring oscillator has been made using single ended inverter stage in 65nm cmos. Two new architectures are proposed to...
This paper presents high speed architecture for AES encryption. The proposed architecture uses integrated unit of encryption in which the consecutive transformations of AES are integrated into a single unit to arrive at an architecture with shorter critical path. Further reduction in critical path is achieved by applying pre-computation technique. Synthesis results using Synopsis 0.18 μιη CMOS process...
With emerging trend in technology wireless networks allow user to travel from one location to another. Mobile Adhoc network (MANET) is one of the subareas of wireless network that dynamically form infrastructure less temporary network. MANET is a collection of intercommunicating mobile nodes forming a temporary network without any centralized administration. Due to the dynamic property of mobile nodes...
This paper presents a high speed architecture for composite field arithmetic based SubBytes transformation (S-box) used in Advanced Encryption Standard (AES) encryption. The proposed architecture is derived by extending the pre-computation technique suggested recently by Liu and Parhi to a recently proposed architecture of AES S-box due to Rashmi, Mohan and Anami. The proposed design of S-box is shown...
This paper is primarily deals the construction of high speed adder circuit using Hardware Description Language (HDL) in the platform Xilinx ISE 9.2i and implement them on Field Programmable Gate Arrays (FPGAs) to analyze the design parameters. The motivation behind this investigation is that an adder is a very basic building block of Arithmetic Logic Unit (ALU) and would be a limiting factor in performance...
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