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In this paper, a multiple-valued DRAM is proposed. Error correction has been used to increase the noise margin of the system. The refresh system is based on series configuration of A/D and D/A converters for each data line. The A/D converters are based on a modular reduction operation, which provides an area efficient design. This memory cell can be used in hardware implementation of multiple valued...
Design and implementation of a novel 16-level multiple-valued memory is proposed. Each memory cell uses equivalent to one binary digit to detect the error due to leakage currents. Moreover, this feature increases the noise margin of the system by a factor of two. The refreshing circuitry is based on a series configuration of A/D and D/A converters for each data line. The error correction and storage...
A novel 16-level current-mode DRAM based on the continuous valued number system (CVNS) representation is introduced. The refreshing circuitry of this DRAM is designed using analogue to digital converter (ADC) and digital to analogue converter modules. Each ADC generates two bits of the output simultaneously which decreases the delay time of the ADC module. Error correction codes are used to increase...
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