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In this work 3D-TCAD simulation is used to investigate and harden single event latch-up (SEL) occurring in embedded SRAMs, in both 130 nm and 65 nm Flash-based Field Programmable Gate Arrays (FPGAs). The methodology to perform accurate SEL simulations on realistic designs suitable for high volume manufacturing is presented. One important new finding is that depending on the technology node, the number...
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