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Embedded memories have become a dominant block in modern SOCs and often constitute more than half the die area. Sense amplifiers are crucial circuits in memories as they are largely responsible for the read operation. The scaling of CMOS technology deep into the sub-micron range has created numerous challenges for SRAMs; notably in that conventional sense amplifier architectures suffer from mismatch...
Reliable cell stability test of modern embedded SRAMs calls for DFT techniques with a flexible detection threshold. We present two programmable cell stability test and debug techniques that use partially discharged floating bit lines to apply a weak overwrite stress to a cell under test. The applied stress can be digitally adjusted to track the process variations or the desired pass/fail threshold...
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