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This paper analyzes the impact of Double Patterning Lithography (DPL) on 6T SRAM variability. A test chip is implemented in a 45nm CMOS process that uses DPL. Measurements from 75 dies demonstrate a significant impact of DPL on SRAM failures. Extensive analysis demonstrates that DPL induced mismatch considerably increases functional failures in SRAM cells, and degrades yield. We also propose a DPL-aware...
For the synthesis of symmetrical linear thinned arrays with a given thinning rate, it would have almost same MSLL solution between taking only segmental aperture nearby both ends of the aperture into account and taking the all aperture into account, at the same time, considering only segmental aperture can reduce the complex computing task remarkably. In this paper, the element distribution characteristic...
Fast changing, increasingly complex, and diverse computing platforms pose central problems in scientific computing: How to achieve, with reasonable effort, portable optimal performance? We present SPIRAL, which considers this problem for the performance-critical domain of linear digital signal processing (DSP) transforms. For a specified transform, SPIRAL automatically generates high-performance code...
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