The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The paper presents design and simulation of, one of the quantum reversible gates, the Feynman gate, using the single electron threshold logic gate. One of the most emerging areas in quantum computing is the application of reversible gates in computational circuits for increasing the computational efficiency. Here the presented approach combines the advantages of the single electron threshold logic...
This paper demonstrates a CMOS Single electron transistor (SET) hybrid arbiter circuit which will act like a communication switch between multiple resources. The proposed architecture combines the merits of CMOS and SET to give a more efficient and compact nanometer scale circuit. The designed arbiter circuit utilizes the Coulomb blockade oscillation characteristics of SET to give better performances...
This paper demonstrates the detailed design of carry look ahead adder with the single electron tunneling based threshold logic. Tunneling is a mechanism in which a single electron can cross a sandwiched structure of insulating layer between two conducting materials known as tunnel junction. The threshold logic works mainly on the basis of the comparison in between the threshold and the weighted sum...
A hybrid SET-CMOS based half subtractor is presented in this paper. Combination of CMOS and SET technology facilitates new advantageous functionalities. The proposed hybrid SET-CMOS based half subtractor is implemented and simulated using T-SPICE. The simulation results are successfully verified with the truth table for the half subtractor. Two different approaches of SET-CMOS hybrid design is explained...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.