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We demonstrate the smallest FinFET SRAM cell size of 0.063 μm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation...
This work demonstrates, for the first time, the reduction of random telegraph noise (RTN) in high-κ/metal gate (HK/MG) stacks incorporated in 22 nm generation FETs. Many thousands of such FETs have been fabricated, measured, and analyzed using a statistical technique to separate RTN as a major noise component from 1/f noise as a minor component. Based on a statistical comparison of these FETs, we...
FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed...
Application of passive voltage contrast at low kV is well-known methodology to identify fault location. In this paper, PVC with high-energy beam instead of at low kV has been performed to one 65 nm technology case and successfully reveals PMOS contact open. The phenomenon and modelling will be further discussed.
We demonstrate 22 nm node technology compatible, fully functional 0.1 mum2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at Vdd=0.9 V. We also present a 0.09 mum2 cell with SNM of 160 mV at Vdd=0.9 V demonstrating the scalability of the design with the same layout. This is the world's smallest 6T-SRAM cell...
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