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This paper presents the technique and results of Single Event Upsets fault injection in the configuration bit-stream of SRAM-based FPGAs through partial reconfiguration of configuration frames. The Xilinx Virtex5 LX50 is used in the experiments. The Single Event Upset controller macro is used injecting faults to random locations of the FPGA bit-stream. The effects were studied on a design consisting...
This paper presents a design for an embedded on board computer that can be used in LEO satellites based on FPGA technology. The design makes use of the multi-core concept provided by modern FPGA's through soft IP cores. The used FPGA is Xilinx V5 FX70, it includes 1 PowerPC 440 processor implemented as hardcore. The rest of processors are Microblaze processors V7.30, implemented as soft IP cores....
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