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High density and small size through silicon via is becoming a research and development hotspot of global academia and industry. The density and size of TSV is often constraint with deep reactive ion etching process, TSV filling process and other process as the diameter of TSV decreases to below 20 micrometer or smaller. In this paper, high density and small size TSV array are fabricated (The diameter...
Through silicon via (TSV) technology is moving in the direction of miniaturization and multi-functional development, and is considered to be the main way beyond Moore's Law. This paper presents a fine-pitch TSV manufacturing method with self-aligned backside insulation layer opening for three-dimensional (3D) integration. It is characterized by the use of chemical-mechanical polished (CMP) process...
In this paper, a novel 3D integration process named Via-Backside-Release process, abbreviated as VBR process, is proposed and technical issues are addressed. With VBR process, there's no need of removal process of copper overburden due to the filling of TSV by copper electroplating, and no individual unit process for producing Cu/Sn microbumps. In order to verify the feasibility of VBR process, a...
TSV interposer provides a cost efficient solution way for 3D IC integration. In this paper, a TSV interposer technology is proposed for SRAM stacking. A simple fabrication process is developed for cost-sensitive application. The mushroomlike Cu/Sn bumps by copper overburden can be directly connected with other substrate, which eliminates a CMP planarization to improve the yield and reduce fabrication...
The fabrication of redistribution layer (RDL) for TSV 3D integration and its optimization are presented in this paper. BCB is selected as the passivation layer and the electroplated Cu is used as the metal layer. CYCLOTENE 3024–46 is utilized and it is deposited by spin-coating and soft cure at 210 °C in annealing oven for 40 minutes with N2 protection. Sputtered Ti/W/Cu and electron beam evaporated...
In this paper, at first electroplating of copper and tin is optimized to fabricate micro-bump. Chip-to-chip bonding process is developed. Then, a temporary bonding process is developed and verified by experiment. And finally, a process for manufacturing multiple layer stacked chip module is designed and prototype of a 4 layer stacked chip module is fabricated successfully.
Though silicon via (TSV) with parylene layer has many advantages, such as low temperature, CMOS matched low-temperature process and so on. In this paper, we use parylene layer as the sidewall to relieve the thermal stress in TSVs. Thermo-mechanical simulation of TSVs is performed to disscuss the effect of the parylene layer. It is found that the introduction of parylene layer can reduce the thermal...
A novel process for ultra-thin (30~50μm) PIN detector fabrication has been developed. The leakage current of all our PIN detectors is found to be less than 6nA at 10V reverse bias. Compared with the leakage current before packaging, the I-V characteristics remain unchanged after the detectors are packaged. The active region get fully depleted at -3V bias, while the breakdown voltage is measured to...
This paper focused on the process of forming sidewall insulation of through silicon via (TSV) which was a challenging bottleneck in 3D integration technologies. In traditional way, etching silicon oxide on via bottom would reduce the thickness of sidewall insulation layer inevitably, which might lead to the failure of TSV sidewall insulation and electrical interconnection characteristic. In this paper,...
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