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High density and small size through silicon via is becoming a research and development hotspot of global academia and industry. The density and size of TSV is often constraint with deep reactive ion etching process, TSV filling process and other process as the diameter of TSV decreases to below 20 micrometer or smaller. In this paper, high density and small size TSV array are fabricated (The diameter...
3D integration with TSVs is emerging as a promising technology for the next generation integrated circuits. TSV filling is a critical process in TSV fabrication and has direct effect on electrical performance of TSVs. In this paper, we mainly focus on effect of additives used in methanesulfonic based solution on copper electroplating filling. Numerical simulation based on an absorption-diffusion model...
In this paper, we present our recent advances in streamlining via-last TSV process flow. Parylene deposition, which is of excellent conformability to the substrate landscape, was introduced into TSV blind via filling process to realize uniform sidewall protection. Simulation was made to analyze the impacts of parylene sidewall on the electric field distribution inside a blind via with high aspect...
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