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InP MZ modulator of sub 1-Vpp driving voltage with quasi-traveling-wave electrode structure and Logic IC of 90-nm CMOS process as its driver were developed. Their applicability was demonstrated through 10-Gb/s - 80-km transmission over full C-band.
We have fabricated a 24 GHz power amplifier (PA) module in a standard 90-nm Si-CMOS process. The PA module consists of two 2-stage cascode configuration PA MMICs and an off-chip Wilkinson power divider and combiner. Each single PA MMIC has a gain of 22 dB with a P3dB output power of 18.3 dBm at 24 GHz load-pull measurement. The fabricated PA module demonstrates state-of-the-art performance, including...
This paper reports a highly linear RF sampler with wide operating frequency range and power supply range. A clock bootstrapping circuit is proposed to decrease both the on-resistance and off-leakage of advanced MOSFETs while considering the device reliability. The proposed RF sampler circuit has been implemented in 90 nm CMOS process, and excellent IIP3 has been obtained at wide frequency range up...
CMOS technology is being advanced rapidly and applications are now expanding into the millimeter-wave regime on a global basis. 60 GHz wireless systems in CMOS have already been reported. In addition, 77 GHz automotive radar is becoming the target for CMOS technology. This paper describes what is believed to be the first transceiver chip for 77 GHz radar in standard 90 nm CMOS.
This paper presents a 20-GHz pseudo-differential power amplifier (PA) fabricated in a standard 90-nm Si-CMOS process. The pseudo-differential PA has a two-stage cascode configuration with differential input and output ports. Assuming the use of an off-chip transformer, the input impedance of each single PA is designed to be 6.25 Omega and the output impedance to be 25 Omega. The individual amplifier...
A heterogeneous multicore SoC (System on a Chip) has been developed for HD (high-definition) multimedia applications that require secure DRM (digital rights management). The SoC integrates three types of processors: two specific-purpose accelerators for a cipher and a high-resolution video decoding; one general-purpose accelerator (MX: Matrix processor); and three CPUs. This is how our SoC achieves...
This paper describes the implementation of 60 and 77GHz PAs in standard 90nm CMOS technology. An accurate transistor model is developed that enables designing circuits operating at frequencies up to 80GHz. The circuits are designed with a unique matching topology for reducing the RF signal loss in matching networks.
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