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A transmit architecture with a programmable 4-tap feedforward equalizer for 6.25 to 12.5 Gb/s serial communications through lossy channels is described. A 16:8-channel MUX/DEMUX chip fabricated in a 0.13 /spl mu/m 7M CMOS process demonstrates a near-end jitter of 16 ps and an equalized far-end jitter of 55 ps at 6.25 Gb/s over a 36'' legacy backplane channel.
A 6.25 Gb/s serial receiver with a 4-tap adaptive DFE is implemented in a 0.13 /spl mu/m 7LM CMOS process. Direct cancellation of the first post-cursor ISI is achieved, enabling recovery of a data eye fully closed from channel losses and crosstalk. A BER<10/sup -15/ is measured over legacy backplane channels.
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