The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We propose pseudo dual-port (DP) SRAM by using 6T single-port (SP) SRAM bitcell with double pumping circuitry, which enables 2-read/write (2RW) operation within a clock cycle. The data sequencer for address/data latch and double output sense amplifier realize the simulations read-read or write-write operation. We designed and implemented a 512-kb pseudo DP SRAM macro based on 28-nm low-power bulk...
With the rapid growth in the market for mobile information terminals such as smart phones and tablets, the performance of image processing engines (e.g., operation speed, accuracy in digital images) has improved remarkably. In these processors, 2-port SRAM (2P-SRAM) macros [1], in which a read port and a write port are operated synchronously in a single clock cycle, are widely used. As shown in Fig...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.